1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the transistors having enhanced performance by using silicon/germanium (Si/Ge) in the drain/source regions so as to enhance charge carrier mobility in the channel region of a PMOS transistor.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements, wherein the field effect transistor may represent an important component in advanced logic circuit designs. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for complex circuitry, such as micro-processors, storage chips and the like, CMOS technology is currently the most promising approach, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, entails a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, with reduced channel length, the controllability of the channel region may be become increasingly difficult, which is also referred to as short channel effects. Hence, various design measures, such as sophisticated dopant profiles, increased capacitive coupling of the gate electrode to the channel region and the like, have been developed, some of which may, however, negatively affect the charge carrier mobility in the channel region. In view of this situation, and since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques, it has been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the above process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating uniaxial tensile strain in the channel region along the channel increases the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity of N-channel transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring new expensive semiconductor materials and manufacturing techniques adapted to these new materials.
An efficient mechanism for enhancing the hole mobility of PMOS transistors may be implemented by forming a strained silicon/germanium layer in the drain and source regions of the P-channel transistors, wherein the compressively strained drain and source regions create uniaxial strain in the adjacent silicon channel region. To this end, the drain and source regions of the PMOS transistors are selectively recessed, while the NMOS transistors are masked and the silicon/germanium layer is subsequently selectively formed in the PMOS transistor by epitaxial growth. Although this technique offers significant advantages in view of performance gain of the PMOS transistor and thus of the entire CMOS device, if an appropriate design is used that balances the performance gain of the PMOS transistor, a performance gain less than expected may be obtained in advanced applications, when higher germanium concentrations are used to further enhance the strain level in the channel region and thus increase the hole mobility.
With reference to FIGS. 1a-1c, a typical process flow will now be described in more detail in order to illustrate the problems involved in the conventional process strategy when using moderately high germanium concentrations.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 which may represent any appropriate carrier material for forming thereon a substantially crystalline silicon layer 102. For instance, the substrate 101 and the semiconductor layer 102 may represent a silicon-on-insulator (SOI) configuration, wherein the semiconductor layer 102 may be directly formed on a respective buried insulating layer (not shown), which may be comprised of any appropriate material, such as silicon dioxide and the like. Furthermore, at this manufacturing stage, the semiconductor device 100 comprises a first transistor 110p and a second transistor 110n, which may represent a P-type transistor and an N-type transistor, respectively. At this manufacturing stage, each of the first and second transistors 110p, 110n may comprise a gate electrode 111, formed on a corresponding gate insulation layer 112, which separates the gate electrodes 111 from respective channel regions 113, which represent a portion of a respective “active region” of the semiconductor layer 102, in which respective drain and source regions are to be formed at a later stage. Thus, the term “active region” in the context of a transistor element is to be understood as a semiconductor region exhibiting a specified dopant profile for adjusting the overall conductivity of the semiconductor material, wherein at least one PN junction may be provided. Furthermore, the respective gate electrodes 111 may have formed on a top surface thereof respective cap layers 104, such as silicon nitride layers and the like.
As previously explained, the performance of P-type transistors may be significantly enhanced by providing a respective silicon/germanium material within the active region of the transistor in order to create a respective strain in the corresponding channel region. In order to appropriately position the silicon/germanium material in the respective active region, the device 100 may be prepared so as to form respective recesses in the first transistor 110p adjacent to the gate electrode 111. For this purpose, respective spacer elements 103S may be provided on the sidewalls of the gate electrode 111 of the transistor 110p in order to provide, in combination with the corresponding cap layer 104, for a reliable confinement of the gate electrode 111 during a subsequent etch process. Since a corresponding recess and a silicon/germanium material may not be required in the N-channel transistor 110n, a corresponding spacer layer 103 may be formed to cover the gate electrode 111 and the respective portions of the semiconductor layer 102 adjacent to the gate electrode 111 in the transistor 110n. Furthermore, a corresponding resist mask 105 may be provided to cover the second transistor 110n, including the spacer layer 103.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of the following processes. After forming respective isolation structures (not shown) and creating a desired vertical dopant profile in the semiconductor layer 102 as is required for the transistor behavior of the first and second transistors 110p, 110n, the gate insulation layer may be formed by deposition and/or oxidation followed by the deposition of an appropriate gate electrode material. Thereafter, sophisticated patterning processes may be performed, which may include advanced photolithography, sophisticated etch techniques and the like in order to obtain the gate electrodes 111 and the gate insulation layers 112. In the same process sequence, the capping layers 104 may also be patterned, which may also be used as an anti-reflective coating (ARC) layer during the respective sophisticated lithography sequences. Thereafter, the spacer layer 103 may be deposited, for instance on the basis of well-established plasma enhanced chemical vapor deposition (PECVD) techniques, thereby providing the spacer layer 103 with an appropriate layer thickness. The spacer layer 103 may be formed on the basis of any appropriate material having a high etch selectivity during a subsequent etch process for forming respective recesses or cavities in the first transistor 110p, for instance, silicon nitride may be efficiently used. Next, the resist mask 105 may be formed using lithography techniques and thereafter an anisotropic etch process 106 may be performed in order to remove the material of the spacer layer 103 from horizontal portions of the first transistor 110p, thereby, creating the spacers 103S, the width of which may thus be substantially determined by the initial layer thickness of the spacer layer 103 and the process parameters of the etch process 106.
Thereafter, a further etch process may be performed on the basis of a well-established etch recipe for removing exposed silicon material from the semiconductor layer 102 selectively to the material of the spacer layer 103 and the spacers 103S. The corresponding etch process may be performed as a substantially anisotropic process or may have a certain degree of isotropy, at least in an advanced phase of the etch process, depending on device requirements. Thus, respective silicon material may be removed, as indicated by the dashed lines, wherein, in an SOI configuration, at least a minimum crystalline silicon material may be maintained, which may act as a growth template during the further processing of the device 100.
FIG. 1b schematically illustrates the semiconductor device 100 at a further advanced manufacturing stage. The semiconductor device 100 is exposed to a deposition ambient 107, in which respective process parameters are appropriately adjusted so as to obtain a selective epitaxial growth of silicon/germanium material 117, wherein a corresponding deposition on dielectric materials, such as the spacer layer 103 and the spacers 103S and the cap layer 104 may be substantially avoided. Consequently, the respective silicon/germanium material may be substantially grown within the previously formed recesses or cavities, wherein the silicon/germanium material 117 may take on substantially the same lattice spacing as the remaining silicon material acting as a growth template. Consequently, after filling the recesses, the corresponding silicon/germanium material 117 may be provided in the form of a strained material, since the natural lattice spacing of silicon/germanium may be slightly greater compared to the silicon lattice spacing. Therefore, a corresponding stress component may be exerted on the channel region 113, thereby creating a respective compressive strain therein. Since the degree of lattice mismatch between the natural lattice spacing of the silicon/germanium material 117 and the silicon material may substantially determine the finally obtained strain in the channel region 113, typically moderately high germanium concentrations of approximately 20 atomic percent or even more may be incorporated into the material 117 in view of further performance gain for the transistor 110p. Thereafter, the respective spacers 103S and the spacer layer 103 may be removed and further manufacturing processes are performed in order to complete the transistor devices 100n, 100p. 
FIG. 1c schematically illustrates the device 100 at a further advanced manufacturing stage. Here, the transistors 110n, 110p may comprise respective drain and source regions 114, which may have any appropriate lateral and vertical dopant profiles in accordance with device requirements. For this purpose, a respective spacer structure 115 may be provided to act as an appropriate implantation mask during preceding implantation sequences for forming the drain and source regions 114. However, in the P-channel transistor 110p, the drain and source regions 114 have a significantly reduced height level compared to the N-channel transistor 110n. The corresponding recess 117R may therefore result in a significantly reduced performance gain or may even result in a reduced performance compared to a device having a lower germanium concentration for otherwise identical design, since generally the amount of strain created in the channel region 113 may be significantly less, since the horizontal stress component provided by the strained silicon/germanium material 117 may be exerted at a significantly lower height level, thereby reducing the corresponding strain prevailing immediately below the respective gate insulation layer 112. Moreover, with the missing silicon/germanium material, a significant amount of dopants may also be lost, thereby further reducing the expected performance gain due to a reduced conductivity of the drain and source regions 114. It turns out that the size of the corresponding recess 117R may be correlated to the amount of concentration of germanium within the material 117, thereby compensating or even overcompensating for the advantageous effect of an increased lattice mismatch between the silicon/germanium material 117 and the initial silicon material at high germanium concentrations.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.